The present invention relates to a dynamic random access memory (DRAM) of a semiconductor memory device, and more particularly to a sense amplifier capable of performing a sensing operation at high speed.
As the more large-scale integration in a semiconductor memory device is recently carried out, a demand for the lower operating voltage or the fast data access speed has increased. In order to meet such a demand, studies on a sensing operation of a bit line playing an important role in the high-speed operation of a memory device, have made most actively progress in field of the memory device. In particular, it is well known fact that the sensing operation of the bit line is dependent on a sensing capability and the operating speed of the sense amplifier.
FIG. 1 shows a circuit diagram of a conventional sense amplifier. The circuit comprises a pair of bit lines 9 and 10 connected to a memory cell array block, first and second p-type sensing transistors 5 and 6 constituting p-type sense amplifier, first and second n-type sensing transistors 7 and 8 constituting n-type sense amplifier, isolation transistors and 2, input/output transistors 3 and 4, and a pair of common input/output lines 11 and 12. If a memory cell connected to the bit lines 9 and 10 is selected by a word line (not shown), a voltage A2 of a control terminal of the isolation transistors 1 and 2 is raised to the logic "high" of a power voltage level. Also a voltage A4 of a control terminal of the input/output transistors 3 and 4 is raised to the logic "high" after the operation of the sense amplifiers 5 to 8, to thus transfer the output of data conveyed on the bit lines 9 and 10 to an exterior of the sense amplifier circuit.
The read operation of FIG. 1 is described with reference to a timing chart in FIG. 2. It should be noted that the bit lines 9 and 10 are precharged to a V.sub.cc /2 level before the memory cell is selected, and a node P1 of a common terminal in the p-type sense amplifier and a node N1 of a common terminal in the n-type sense amplifier are also precharged to the V.sub.cc /2 level by the voltages A1 and A3 of the control terminals, respectively. In this case, the voltages A1 and A3 of the control terminals are power sources supplying a potential of the V.sub.cc /2 level. However, when the memory cell is selected, the voltages A1 and A3 of the control terminals respectively provide a power voltage V.sub.cc and a ground voltage V.sub.ss level, by a row address strobe RAS signal. Then, the voltage level of the node N1 is shifted from the V.sub.cc /2 level to the ground voltage level, and the n-type sense amplifier drops the bit line close to the ground voltage level to the ground voltage level. After a given time is passed, the p-type sense amplifier operates and raises the bit line close to the power voltage level to the power voltage level. However, since sensing nodes SAN and SAN are initially precharged to the V.sub.cc /2 level, the charge sharing between the bit lines connected to both sides of the isolation transistors 1 and 2 is considerably delayed, and the variation speed of a potential difference between the bit lines 9 and 10 becomes extremely slow, because of the loading of the bit lines. This leads to a delay of time, the time being that the input/output transistors 3 and 4 are turned on when the potential difference between the bit lines 9 and 10 is approximately 1 V, thereby, the access time of the data becomes slow.
FIG. 3 shows a circuit diagram of another conventional sense amplifier. The circuit is constructed so that array blocks 40 and 45 neighboring to each other share an n-type sense amplifier, input/output transistors 31 and 32, and common input/output lines 35 and 36. Thus, when the array block 40 is selected, a voltage B5 of a control terminal of isolation transistors 23 and 24 is shifted to 0 V, thereby isolating the array block 45 from the shared components. In the same way, when the right array block 45 is selected, a voltage B2 of a control terminal of the isolation transistors 21 and 22 is shifted to 0 V. The circuit of FIG. 3 is greatly improved in view of the degree of integration, in comparison with the circuit of FIG. 1. However, it still has a disadvantage in that the high speed sensing operation is difficult since the sensing operation of the bit line and the transferring operation of data to the common input/output lines 35 and 36, are performed in the same method as that of the circuit of FIG. 1.